 | Hassen AZIZA |
| IM2NP - Polytech Dpt Microélectronique et Télécommunications 38, rue Frédéric Joliot-Curie IMT Technopôle de Château Gombert 13451 Marseille Cedex 20 France | |
| téléphone : +33 (0)4 91 05 47 84 | |
| mail : hassen.aziza@im2np.fr |
| | Hassen AZIZA |
| IM2NP - Polytech Dpt Microélectronique et Télécommunications 38, rue Frédéric Joliot-Curie IMT Technopôle de Château Gombert 13451 Marseille Cedex 20 France | |
| téléphone : +33 (0)4 91 05 47 84 | |
| mail : hassen.aziza@im2np.fr |
Publications :
Aziza H., Plantier J., Portal J-M., “A Realistic Fault Simulation Model for EEPROM Memories”, IEEE Proceedings of International Workshop For Design & Test, IDT’09, Arabie Saoudite, 2009, accepted for publication.
Aziza H., Perez A., Bergeret E., “Analog Blocks Design Automation”, Journal of WSEAS transactions on circuits and systems (WSEAS), Vol. 8, N° 8, 2009, pp.686-695.
Aziza H., Pannier P., “An access control solution based on NFC compliant cell phones”, Web proceeding of SmartMobility conference, SmartEvent’09, Sophia Antipolis, France, 2009, pp.1-6.
Plantier J., Aziza H., Portal J.M., Reliaud C., “Investigation of EEPROM memories reliability during endurance and retention tests”, IEEE Proceedings of International Conference on Design & Technology of Integrated Systems in Nanoscal Era, DTIS’09, Egypt, 2009, pp.241-246.
Ginez O., Portal J-M., Aziza H., “An on-line testing scheme for repairing purposes in Flash memories”, IEEE Proceedings of International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS '09, Czech Republic, 2009, pp.120-123.
Riguaud F., Portal J.M., Dreux P., Vast J., Aziza H., Bas G., “Fast Embedded Characterization of FEOL Variations in MOS Devices”, Microelectronic Test Structures, IEEE Proceedings of International Conference on Microelectronic Test Structures, ICMTS’09, Japon, 2009, pp.205-2008.
Aziza H., Plantier J., Portal J.M., Relliaud C., Ginez O., Née D., “A novel Diagnosis Methodology Based On I-V Signatures Extraction”, IEEE Proceedings of Non Volatile Memory Technology Symposium, NVMTS’08, USA, 2008, pp.1-6.
Aziza H., Bergeret E., Pérez A., “A novel Design Methodology for Current Reference Circuits”, IEEE Proceedings of International Conference on Electronics, Circuits and Systems, ICECS’08, Malte, 2008, pp.238-241.
Aziza H., Portal J-M., Ginez O., Bergeret E., “An Efficient Diagnosis Methodology for Charge Pump Circuits: Application to Flash EEPROM devices”, IEEE Proceedings of International Conference on Design & Technology of Integrated Systems in Nanoscal Era, DTIS’08, Tunisie, 2008, pp.1-6.
Aziza H., Bergeret E., Portal J.M., Ginez O., “A Low-Power Oriented Design Methodology for Analog Blocks”, Journal of Low Power Electronics (JOLPE), Vol. 4 N° 1, pp.60-67, 2008.
Aziza H., Delsuc B., “Device and Memory array Models for Flash EEPROM Technology”, Journal of WSEAS transactions on circuits and systems (WSEAS), Vol. 7, N° 4, pp.249-258, 2008.
Aziza H., Portal J-M., Ginez O., Bergeret E., “An efficient Diagnosis Methodology for analog blocks: Application to Current Reference Circuits”, Proceedings of the European Test Symposium, ETS’08, Italie, 2008.
Aziza H., Portal J.M., Née D., Reliaud C., Argoud F., “Peripheral Circuitry Impact on EEPROM Threshold Voltage”, IEEE Non Volatile Memory Technology Symposium, NVMTS’07, USA, 2007, pp.20-24.
Aziza H., Bergeret E., Pérez A., “An Automated Design Methodology for Charge Pump Circuits”, IEEE Proceedings of International Conference on Electronics, Circuits and Systems , ICECS’07, Maroc, 2007, pp.108-113.
Aziza H., Bergeret E., Pérez A., Portal J.M., “An Efficient Charge Pump Model to Evaluate Impact of Design parameters on Charge Pump Circuits Performances: Application on RFID circuits”, IEEE Proceedings of Design & Test of Integrated Systems, DTIS’07, Maroc, 2007, pp.112-117.
Ginez O., Portal J-M., Aziza H., “A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories”, Proceedings of the IEEE International Test Conference, ITC’08, USA, 2008, pp.1-10.
Rigaud F., Portal J.M., Aziza H., Nee D., Vast J., Argoud F., Borot B., “Mixed test structure for soft and hard defect detection”, IEEE Proceedings of International Conference on Microelectronic Test Structures, ICMTS’08, Japon, 2008, pp.52-55.
Ginez O., Portal J-M., Aziza H., “Reliability Issues in Flash Memories: An On-Line Diagnosis and Repair Scheme for Word Line Drivers”, Proceedings of Memory Technology and Design conference, ICMTD’08, pp.1-6, France, 2008.
Rigaud F., Portal J.M., Aziza H., Née D., Vast J., Auricchio C., “Test Structure for Process and Product Evaluation”, Proceedings of the IEEE International Conference on Microelectronic Test Structures, ICMTS’07, Japon, 2007, pp.140-144.
Rigaud F., Portal J.M., Aziza H., Née D., Vast J., Argoud F., Borot B., “Mixed Test Structure for Soft and Hard Defect Detection”, Proceedings of the 2nd IEEE International Workshop on Design for Manufacturability and Yield, DFMY’07, USA, 2007.
Rigaud F., Portal J.M., Aziza H., Née D., Vast J., Auricchio C., “Test Structure for Process and Product Performances Evaluation”, Proceedings of the 1st IEEE International Workshop on Design for Manufacturability and Yield, DFMY’06, USA, 2006.
Aziza H., Delsuc B., Portal J.M., Née D., “Speeding up simulation time in EEPROM memory designs”, Proceedings of the Design & Test of Integrated Systems, DTIS’06, Tunisie, 2006, pp.285-288.
Regnier A., Portal J.M., Aziza H., Masson P., Bouchakour R., Relliaud C., Née D., Mirabel J.M., “EEPROM Compact Model with SILC Simulation Capability”, IEEE Non Volatile Memory Technology Symposium, NVMTS’06, USA, 2006, pp26-30.
Portal J.M., Aziza H., Née D, “EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement”, Journal of Electronic Testing (JETTA), Vol. 21, 2005, pp.33-42.
Aziza H., Portal J.M., Née D., “EEPROM Threshold Current Extraction: Silicon Validation”, Proceedings of the European Test Symposium, ETS’04, France, 2004, pp.81-87.
Portal J.M., Forli L., Aziza H., Nee D., Borot B., “BEOL Diagnosis based on Ring Oscillator Characterization”, 2nd IEEE International Workshop on Infrastructure IP, I-IP’04, USA, 2004.
Portal J.M., Aziza H., Née D, “EEPROM Memory: Threshold Voltage Built In Self Diagnosis”, Proceedings of the IEEE International Test Conference, ITC’03, USA, 2003, pp.23-28.
Portal J.M., Aziza H., Née D, “EEPROM Memory Diagnosis Based on Threshold Current Extraction”, Proceedings of the IEEE Conference on Design of Circuits and Integrated Systems, DCIS’03, Espagne, 2003, pp.133-139.
Portal J.M., Aziza H., Née D, “EEPROM Memory: Threshold Voltage Built In Self Diagnosis”, Proceedings of the IEEE European Test Workshop, ETW’03, Hollande, 2003, pp.81-87.
Portal J.M., Forli L., Aziza H., Née D, “An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell”, Proceedings of the IEEE International Test Conference, ITC’02, USA, 2002, pp.31-36.
Portal J.M., Forli L., Aziza H., Née D, “An Automated Design Methodology for EEPROM Cell (ADE)”, Proceedings of the IEEE International Workshop on Memory Technology Design and Testing, MTDT’02, France, 2002, pp.137-142.
Portal J.M., Forli L., Aziza H., Née D, “An Automated Geometric Defect Diagnosis Methodology for EEPROM Cell (AGDE)”, Proceedings of the IEEE European Test Workshop, ETW’02, Grèce, 2002, pp.343-344.
Concours internationaux
Aziza H., Benarbia V., Inoztrosa I., Lauréat (médaille d’argent) au concours international SIMagine. Ce concours international récompense les solutions innovantes dans le domaine des applications embarquées sur cartes à puce (SIMcard).
Référencé sur le site de la société Gemalto, premier fabricant de cartes à puces : http://www.gemalto.com/simagine/.
Nombreux articles de presse : http://www.strategiestm.com/Gemalto-recompense-l-innovation.html; http://www.servicesmobiles.fr/services_mobiles/3_gsm/page/2/; http://www.smartcardstrends.com/det_atc.php?idu=8812....
Brevets
Portal J.M., Forli L., Aziza H., L2MP - ST Microelectronics, Née D, Procédé de modélisation mathématique de composants électroniques et son utilisation pour la simulation, la détermination de géométrie et le diagnostic de défauts dans le composant, N° de dépôt 0208652, N° de dossier 02-RO-029.
Portal J.M., Aziza H., Née D, L2MP - ST Microelectronics, Circuit de caractérisation des tensions de seuils dans les mémoires non volatiles sous format numérique et traitement en vue du diagnostic des données obtenues, N° de dépôt 0306184, N° de dossier 03-RO-059.
