Daniela Munteanu
IM2NP
Bât. IRPHE
49, rue Joliot Curie - BP 146
Technopôle de Château - Gombert
13384 Marseille Cedex 13
France
téléphone : + 33 (0) 4 13 55 20 49
fax : +33 (0) 4 13 55 20 01
mail : daniela.munteanu@im2np.fr

Chargée de recherche CNRS, Jeune chercheur CNRS-STIC (ATIP 2OO2)


Domaines d'activité :

Microélectronique. Caractérisation électrique, modélisation et simulation.
Matériaux et dispositifs Silicium-Sur-Isolant (SOI). Transistor MOS ultime.
Dispositifs innovants sur SOI. Transport non-stationnaire et balistique.
Effets quantiques. Phénomènes transitoires dans les dispositifs SOI.


Publications récentes :

Cristoloveanu S., D. Munteanu, M. Liu.- A review of the pseudo-MOS transistor in SOI wafers : operation, parameter extraction, and applications.- IEEE Transactions on Electron Devices, vol. 47, n° 5, p. 1018-1027, 2000

Cristoloveanu S., T. Ernst, D. Munteanu, T. Ouisse.- Ultimate MOSFET on SOI : ultra-thin, single gate, double gate or ground plane.- International Journal of High Speed Electronics and Systems, vol. 10, n° 1, p. 217-230, 2000

Munteanu D., G. Le Carval, G. Guegan.- Non-stationary transport effects: impact on performances of realistic 50nm MOSFET technology.- The TCAD Driven CAD Journal, vol. 11, no. 11, p. 7-9, 2000

Munteanu D., Le Carval G., Fenouillet-Beranger C., Faynot O., Pelloie J.L.- Non-stationary transport effects : impact on 0.1µm PD SOI technology.- Proceedings of the 2000 IEEE International SOI Conference, IEEE, p. 58-59, 2000

Ionescu A.M., Munteanu D.- A novel in situ characterization technique : the SOI intrinsic point-probe MOSFET.- IEEE Electron Device Letters, vol. 22, n° 4, p. 166-169, 2001

Masson P., Autran J.L., Munteanu D.- DYNAMOS : a numerical MOSFET model including quantum-mechanical and near-interface trap transient effects.- Second European Workshop ULIS, F. Balestra (ed), Editions INPG, Grenoble, p. 109-112, 2001

Munteanu D., Le Carval G., Fenouillet-Beranger C.- Analysis of non-stationary transport and quantum effects in realistic 0.1µm partially-depleted SOI technology.- Proceedings of the Tenth International Symposium on Silicon-On-Insulator Technology and Devices, Electrochemical Society Meeting (ECS), Electrochemical Society, vol. 2011-3, p. 199-204, 2001

Munteanu D., Le Carval G., Guegan G.- Impact of non-stationary transport effects on realistic 50nm MOS technology.- Proceedings of the Fourth International Conference on Modeling and Simulation of Microsystems (MSM'2001), M. Laudon and B. Romanowicz (eds.), Computational Publications, p. 462-465, 2001

Munteanu D., Le Carval G., Guegan G.- Non-stationary transport effects : impact on performances of realistic 50nm MOSFET technology.- Proceedings of the 2nd European Workshop on Ultimate Integration of Silicon (ULIS'2001), F. Balestra (ed.), Editions INPG, Grenoble, p. 105-108, 2001

Munteanu D., O. Rozeau, S. Cristoloveanu, J. Jomaah, J. Boussey, M. Wetzel, P. de la Houssaye, I. Lagnado.- Enhanced performance SOS materials and devices for RF applications.- Journal of the Electrochemical Society, vol. 148, n° 4, p. 218-224, 2001

Autran J.L. (ed), Munteanu D. (ass. ed).- Proceedings of the 6th European Conference "Radiation and its Effects on Components and Systems" (RADECS 2002), Proceedings IEEE 01TH8605C (The Institute of Electrical and Electronics Engineers), 2002

Autran J.L. (guest ed), Munteanu D. (ass. ed).- IEEE Transactions on Nuclear Science, Special Issue, vol. NS-49, n° 3, June 2002

Ionescu A.M., Munteanu D.- New compact model for generation drain current transients in weak and moderate inversion regimes of submicron floating-body PD SOI MOSFETs.- Proceedings of the 5th International Conference on Modeling and Simulation of Microsystems (MSM'2002), Puerto Rico, USA, 22-25 April 2002, p. 754-758, 2002

Masson P., Autran J.L., Munteanu D.- DYNAMOS : a numerical MOSFET model including quantum-mechanical and near-interface trap transient effects.- Solid State Electronics, vol. 46, p. 1051-1059, 2002

Munteanu D., Autran J.L.- Two-dimensional modeling of quantum ballistic transport in ultimate double-gate SOI devices.- Proceedings of the 3rd European Workshop on Ultimate Integration of Silicon (ULIS 2002), Munich, Germany, 7-8 March 2002, à paraître, 2002

Munteanu D., G. Le Carval, G. Guegan.- Impact of technological parameters on non-stationary transport in realistic 50nm MOS technology.- Solid State Electronics, vol. 46, p. 1045-1050, 2002

Munteanu D., G. Le Carval, G. Guegan.- Investigation of non-stationary transport and quantum effects in realistic deep submicron partially-depleted SOI technology.- Electrochemical and Solid State Letters, vol. 5, n° 5, p. G29-G31, 2002

Munteanu D., Ionescu A.M.- Modeling of drain current overshoot and recombination lifetime extraction in floating-body submicron SOI MOSFETs.- IEEE Transactions on Electron Devices, vol. 49, p. 1198-1205, 2002

Munteanu D., Le Carval G.- Assessment of anomalous behavior in hydrodynamic simulation of CMOS bulk and partially-depleted SOI devices.- Journal of the Electrochemical Society, vol. 149, p. G574-G580, 2002

Autran J.L. and Munteanu D. - Tunneling component of the ballistic current in ultimate double-gate devices. - Electrochemical and Solid-State Letters, vol. 6, p. G95-G97, 2003

Autran J.L., Munteanu D., Dinescu R. and Houssa M. - Stretch-out of high-permittivity MOS capacitance voltage curves resulting from a lateral non-uniform oxide charge distribution. - Journal of Non-Crystalline Solids, vol. 322, n°  1-3, p. 219-224, 2003

Autran J.L., Munteanu D.- Les architectures innovantes sur silicium mince : un second souffle pour la loi de Moore ? Revue de l’Electricité et de l’Electronique, n° 8, p. 21-31, 2003

Bescond M., Autran J.L., Munteanu D., Lannoo M.- Atomic-scale modeling of Double-Gate, MOSFETs using a tight-binding Green’s function formalism.- Solid-State Electronics, vol. 48, p. 567-574, 2004

Ionescu A. M., Munteanu D., Hefyene N., Anghel C.- Compact modeling of weak inversion generation transients in SOI MOSFETs.- Journal of the Electrochemical Society, vol. 151, p. G396-G401, 2004

Autran J.L., Munteanu D., Houssa M.- Electrical characterization, modeling and simulation of high-k based MOS devices.- in “Fundamental and Technological Aspects of High-k Gate Dielectrics”, M. Houssa (ed), Institute of Physics Publishing, London, Chapter 3.4, p. 251-289, 2004

Autran J.L., Aubert M., Tintori O., Munteanu D., Decarre E.- An analytical subthreshold current model for ballistic double-gate MOSFETs.- Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, vol. 2, p. 171-174, 2004

Autran J.L., Munteanu D., Houssa M.- Electrical modeling and simulation of nanoscale MOS devices with a high-permittivity dielectric gate stack.- Material Research Society Symposium Proceedings, vol. 811, p. D6-1, 2004

Autran J.L., Munteanu D., Tintori O., Harrison S., Decarre E., Skotnicki T.- Quantum-mechanical analytical modeling of threshold voltage in long-channel double-gate MOSFET with symmetric and asymmetric gates.- Technical Proceedings of the 2004 NSTI Nanotechnology Conference and Trade Show, vol. 2, p. 163-166, 2004

Bescond M., Autran J.L., Cavassilas N., Munteanu D., Lannoo M.- Treatment of point defects in nanowire MOSFETs using the nonequilibrium Green's function formalism.- Proceedings of the 10th IEEE International Workshop on Computational Electronics (IWCE10), Purdue University, Indiana, USA, p. 84-85, 2004

Bescond M., Néhari K., Autran J.L., Cavassilas N., Munteanu D., Lannoo M.- 3D quantum modeling and simulation of multi-gate nanowire MOSFETs.- Proceedings of the 50th IEEE International Electron Device Meeting (IEDM 2004), San Francisco, Etats-Unis, p. 617-620, 2004

Castellani-Coulié K., Munteanu D., Ferlet-Cavrois V., Autran J.L.- Simulation analysis of the bipolar amplification in fully-depleted SOI technologies under heavy-ion irradiations.- Proceedings of the European Workshop on Radiation and its Effects on Components and Systems (RADECS’2004), Madrid, Espagne, p. 127-130, 2004

Harrison S., Coronel P., Leverd F., Cerutti R., Palla R., Delille D., Borel S., Pantel R., Dutartre D., Morand Y., Samson M.P., Lenoble D., Talbot A., Boeuf F., Sanquer M., Jehl X., Bustos J., Brut H., Cros A., Munteanu D., Autran J.L., Skotnicki T.- High performance SON (Silicon-On-Nothing) double gate MOSFET with perfect electrostatic integrity for nanoscale regime.- Proceedings of the 2004 IEEE Silicon Nanoelectronic Workshop (SNW’2004), Honolulu, Hawaii, USA, p. 3-4, 2004

Harrison S., Cros A., Coronel P., Leverd F., Beverina A., Cerutti R., Wacquez R., Bustos J., Delille D., Tavel B., Barge D., Bienacel J., Samson MP., Martin F., Maitrejean S., Munteanu D., Autran J.L., Skotnicki T.- Poly-Gate REplacement Through Contact Hole (PRETCH): A new method for high-k/metal gate and multi-oxide implementation on chip.- Proceedings of the 50th IEEE International Electron Device Meeting (IEDM 2004), San Francisco, Etats-Unis, p. 291-294, 2004

Harrison S., Munteanu D., Autran J.L., Cros A., Cerutti R., Skotnicki T.- Electrical characterization and modeling of high-performance SON DG MOSFETs.- Proceedings of the 34th European Solid State Device Research Conference (ESSDERC’2004), Leuven, Belgique, p. 373-376, 2004

Munteanu D., Autran J.L., Bescond M., Houssa M.- Impact of high-k gate dielectric on decananometer double-gate MOSFETs : gate-fringing field and parasitic charge effects.- Proceedings of the 5th European Workshop on Ultimate Integration of Silicon (ULIS 2004), Leuven, Belgium, p. 39-42, 2004

Autran J.L., Decarre E., Munteanu D., Bescond M., Houssa M.- A simulation analysis of FIBL in decananometer double-gate MOSFETs with high-κ gate dielectrics.- Journal of Non-Crystalline Solids, vol. 351, p. 1897-1901, 2005

Autran J.L., Munteanu D., Houssa M., Castellani-Coulié K., Said A.- Performance degradation induced by fringing field-induced barrier lowering and parasitic charge in double-gate metal-oxide-semiconductor field-effect transistors with high-κ dielectrics.- Japanese Journal of Applied Physics, p. 8362-8366, 2005

Autran J.L., Munteanu D., Tintori O., Aubert M., Decarre E.- An analytical subthreshold current model for ballistic quantum-wire MOS transistors.- Molecular Simulation, vol. 31, n° 2-3, p. 179-183, 2005

Autran J.L., Nehari K., Munteanu D.- Compact modeling of the threshold voltage in silicon nanowire MOSFET including 2D-quantum confinement effects.- Molecular Simulation, vol. 31, p. 839-843, 2005

Bescond M., Autran J.L., Cavassilas N., Munteanu D., Lannoo M.- Treatment of point defects in nanowire MOSFETs using the nonequilibrium Green’s function formalism.- Journal of Computational Electronics, vol. 3, p. 393-396, 2005

Castellani-Coulié K., Munteanu D., Autran J.L., Ferlet-Cavrois V., Paillet P., Baggio J.- Simulation analysis of the bipolar amplification induced by heavy-ion irradiation in double-gate MOSFETs.- IEEE Transactions on Nuclear Science, vol. NS-52, p. 2137- 2143, 2005

Castellani-Coulié K., Munteanu D., Ferlet-Cavrois V., Autran J.L.- Simulation analysis of the bipolar amplification in fully-depleted SOI technologies under heavy-ion irradiations.- IEEE Transactions on Nuclear Science, vol. NS-52, p. 1474-1479, 2005

Munteanu D., Autran J.L., Harrison S.- Quantum short-channel compact model for the threshold voltage in double-gate MOSFETs with high-κ gate dielectrics.- Journal of Non-Crystalline Solids, vol. 351, p. 1911-1918, 2005 2005

Munteanu D., Autran J.L., Harrison S., Nehari K., Tintori O., Skotnicki T.- Compact model of the quantum short-channel threshold voltage in symmetric Double-Gate MOSFET.- Molecular Simulation, vol. 31, p. 831-837, 2005

Castellani-Coulié K., D. Munteanu, J.L. Autran, V. Ferlet-Cavrois, P. Paillet, J. Baggio. Investigation of 30nm gate-all-around MOSFET sensitivity to heavy ions: a 3-D simulation study. IEEE Transactions on Nuclear Science, vol. 53, n° 4, p. 1950-1958, 2006

Castellani-Coulié K., D. Munteanu, J.L. Autran, V. Ferlet-Cavrois, P. Paillet, J. Baggio. Analysis of 45nm multi-gate transistors behavior under heavy ion irradiation by 3D device simulation. IEEE Transactions on Nuclear Science, vol. 53, n° 6, p. 3265-3270, 2006

Munteanu D., J.L. Autran, X. Loussier, S. Harrison, R. Cerutti, T. Skotnicki. Quantum short-channel compact modeling of drain-current in double-gate MOSFET. Solid State Electronics, vol. 50, n° 4, p. 680-686, 2006

Nehari K., Cavassilas N., Autran J.L., Bescond M., Munteanu D., Lannoo M. Influence of band-structure on electron ballistic transport in silicon nanowire MOSFET’s : an atomistic study. Solid State Electronics, vol. 50, n°4, p. 680-686, 2006

Autran J.L. and Munteanu D. Au-delà du transistor MOS sur silicium massif : Nouveaux matériaux, architectures innovantes et dispositifs ultimes. Revue d'Electricité et de l'Electronique, n° 4, p. 25-37, 2007

Autran J.L., Roche P., Borel J., Sudre C., Castellani-Coulié K., Munteanu D., Parrassin T.,  Gasiot G., Schoellkopf J.P. Altitude SEE Test European Platform (ASTEP): project overview, first results in CMOS 130 nm and perspectives. IEEE Transactions on Nuclear Science, vol. 54, n° 4, p. 1002-1009, 2007

Barral V., Poiroux T., Vinet M., Widiez J., Previtali B., Grosgeorges P., Le Carval G., Barraud S., Autran J.L., Munteanu D., Deleonibus S. Experimental determination of the channel backscattering coefficient on 10 to 70 nm- metal-gate double-gate transistors. Solid State Electronics, vol. 51, n° 4, p. 537–542, 2007

Loussier X., Munteanu D., Autran J.L. Impact of high-permittivity dielectrics on speed performances and power consumption in double-gate-based CMOS circuits. Journal of Non-Crystalline Solids, vol. 353, p. 639–644, 2007

Munteanu D., Autran J-L., Ferlet-Cavrois V., Paillet P., Baggio J., Castellani-Coulié K. 3D quantum numerical simulation of single-event transient in multiple-gate nanowire MOSFETs. IEEE Transactions on Nuclear Science, vol. 54, n° 4, p. 994-1001, 2007

Munteanu D., J.L. Autran, X. Loussier, S. Harrison, R. Cerutti. Compact modeling of symmetrical double-gate MOSFETs including carrier confinement and short-channel effects. Molecular Simulation, vol. 33, n° 7, p. 605-611, 2007

Autran J.L. and Munteanu D. Simulation of electron transport in nanoscale independent-gate double-gate devices using a full 2D Green’s function approach. Journal of Computational and Theoretical Nanoscience, vol. 5, p. 1120–1127, 2008

Loussier X., Munteanu D., Autran J.L., Tintori O. Impact of geometrical and electrical parameters on speed performances in ultimate double-gate metal-oxide-semiconductor field-effect transistor. Japanese Journal of Applied Physics, vol. 47, n° 5, p. 3390-3395, 2008

Martinie S., Le Carval G., Munteanu D., Soliveres S., Autran J.L. Impact of ballistic and quasi-ballistic transport on performances of double-gate MOSFET-based circuits. IEEE Transactions on Electron Devices, vol. 55, no. 9, p. 2443-2453, 2008

Moreau M., Munteanu D. and Autran J.L. Simulation analysis of quantum confinement and short-channel effects in independent double-gate metal-oxide-semiconductor field-effect transistors. Japanese Journal of Applied Physics, vol. 47, no. 9, p. 7013-7018, 2008

Munteanu D. and Autran J.L. Modeling and simulation of single-event effects in digital devices and Ics. IEEE Transactions on Nuclear Science, vol. 55, no. 4, p. 1854-1878, 2008

Barral V., Poiroux T., Barraud S., Bonno O., Andrieu F., Faynot O., Munteanu D., Autran J.L. and Deleonibus S. Evidences on the physical origin of the unexpected transport degradation in ultimate n-FDSOI devices. IEEE Transactions on Nanotechnology, in press, 2009

Barral V., Poiroux T., Bournel A., Munteanu D., Autran J.L. and Deleonibus S. Experimental investigation on the quasi-ballistic transport: part I- Determination of a new backscattering coefficient extraction methodology. IEEE Transactions on Electron Devices, in press, 2009

Barral V., Poiroux T., Munteanu D., Autran J.L. and Deleonibus S. Experimental investigation on the quasi-ballistic transport: Part II- Backscattering coefficient extraction and link with the mobility. IEEE Transactions on Electron Devices, in press, 2009

Martinie S., Le Carval G., Munteanu D., Autran J.L. New unified analytical model of backscattering coefficient from low to high field conditions in quasi-ballistic transport. IEEE Electron Device Letters, in press, 2009


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